Fix initialization with CH340 UARTs

Initialization is messed up with older Linux kernels and that
results in 9600 baud being used unconditionally. Setting the baud
rate separately seems to work around this successfully.

README.md

@@ -27,11 +27,15 @@ So far, stcgal was tested with the following MCU models:
 * STC89C52RC (BSL version: 4.3C)
 * STC12C2052AD (BSL version: 5.8D)
 * STC12C5A60S2 (BSL version: 6.2I)
+* STC11F02E (BSL version: 6.5K)
 * STC11F08XE (BSL version: 6.5M)
 * STC15F104E (BSL version: 6.7Q)
 * STC15F204EA (BSL version: 6.7R)
 * STC15L104W (BSL version: 7.1Q)
 * IAP15F2K61S2 (BSL version: 7.1S)
+* STC15L2K16S2 (BSL version: 7.2.4S)
+* STC15W408AS (BSL version: 7.2.4T)
+* STC15W4K56S4 (BSL version: 7.3.4T)
 
 More compatibility testing is going to happen soon.
 
@@ -229,6 +233,7 @@ Option key                    | Possible values   | Protocols/Models    | Descri
 ```rstout_por_state```        | low/high          | STC15+              | RSTOUT pin state after power-on reset
 ```uart2_passthrough```       | true/false        | STC15+              | Pass-through UART1 to UART2 pins (for single-wire UART mode)
 ```uart2_pin_mode```          | push-pull/normal  | STC15+              | Output mode of UART2 TX pin
+```cpu_core_voltage```        | low/mid/high      | STC15W+             | CPU core voltage (low: ~2.7V, mid: ~3.3V, high: ~3.6V)
 
 ### Frequency trimming
 

debian/changelog

@@ -0,0 +1,5 @@
+stcgal (1.0git) unstable; urgency=low
+
+  * Initial Debianized Release
+
+ -- Andrew 'Necromant' Andrianov <andrew@ncrmnt.org>  Wed, 25 Nov 2015 13:07:03 +0300

debian/compat

@@ -0,0 +1 @@
+9

debian/control

@@ -0,0 +1,27 @@
+Source: stcgal
+Section: electronics
+Priority: optional
+Maintainer: Andrew Andrianov <andrew@ncrmnt.org>
+Build-Depends: debhelper (>= 9), python3, python3-setuptools, dh-python
+Standards-Version: 3.9.5
+Homepage: https://github.com/grigorig/stcgal
+X-Python3-Version: >= 3.2
+
+Package: stcgal
+Architecture: all
+Depends: ${misc:Depends}, python3, python3-serial
+Description: STC MCU ISP flash tool
+ stcgal is a command line flash programming tool for STC MCU Ltd. 8051
+ compatible microcontrollers. The name was inspired by avrdude.
+ .
+ STC microcontrollers have a UART based boot strap loader (BSL). It
+ utilizes a packet-based protocol to flash the code memory and
+ IAP memory over a serial link. This is referred to as in-system
+ programming (ISP). The BSL is also used to configure various
+ (fuse-like) device options. Unfortunately, this protocol is not
+ publicly documented and STC only provide a (crude) Windows GUI
+ application for programming.
+ .
+ stcgal is a full-featured Open Source replacement for STC's Windows
+ software; it supports a wide range of MCUs, it is very portable and
+ suitable for automation.

debian/copyright

@@ -0,0 +1,32 @@
+Format: http://www.debian.org/doc/packaging-manuals/copyright-format/1.0/
+Upstream-Name: stcgal
+Upstream-Contact: Grigori Goronzy <greg@kinoho.net>
+Source: https://github.com/grigorig/stcgal
+
+Files: *
+Copyright: 2013-2015 Grigori Goronzy <greg@kinoho.net>
+License: MIT
+
+Files: debian/*
+Copyright: 2015 Andrew 'Necromant' Andrianov <andrew@ncrmnt.org>
+           2015 Grigori Goronzy <greg@kinoho.net>
+License: MIT
+
+License: MIT
+ Permission is hereby granted, free of charge, to any person obtaining a copy
+ of this software and associated documentation files (the "Software"), to deal
+ in the Software without restriction, including without limitation the rights
+ to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ copies of the Software, and to permit persons to whom the Software is
+ furnished to do so, subject to the following conditions:
+ .
+ The above copyright notice and this permission notice shall be included in all
+ copies or substantial portions of the Software.
+ .
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ SOFTWARE.

debian/docs

@@ -0,0 +1,2 @@
+README.md
+TODO.md

debian/rules

@@ -0,0 +1,7 @@
+#!/usr/bin/make -f
+
+export PYBUILD_NAME=stcgal
+
+%:
+	dh $@ --with python3 --buildsystem=pybuild
+

debian/source/format

@@ -0,0 +1 @@
+3.0 (native)

doc/stc15-options.txt

@@ -5,6 +5,7 @@ MCS3 is like early STC15 MCS1.
 MCS2 is like early STC15 MCS2.
 MCS4 is like early STC15 MCS0 but with additions.
 MCSX is like early STC15 MCS12.
+MCSY is new in STC15W4 series
 
 baseline
 B5 FF F7 BB 9F
@@ -80,3 +81,37 @@ external oscillator enabled (IAP15F2K61S2)
 external oscillator enabled + clock gain low (IAP15F2K61S2)
 9C 7F F7 BB 9C
 --> MCS 4 bit controls clock gain. high => high clock gain, low => low clock gain.
+
+
+cpu core supply level (MCSY)
+
+in status packet:
+
+2.68v
+46 B9 68 00 34 50 8D FF 73 96 F7 BC 9F 00 5B 7A C0 FD 27 ED 00 00 73 54 00 F5 28 04 06 70 96 02 15 19 1C 1E 23 00 EC E0 04 D7 EA 92 FF FF FF 15 09 25 60 14 BD 16
+
+3.33v
+46 B9 68 00 34 50 8D FF 73 96 F7 BC 9F 00 5B 92 30 FD 25 EA 00 FC 73 54 00 F5 28 04 06 70 96 02 15 19 1C 1E 23 00 EC E0 04 D7 F7 92 FF FF FF 15 09 25 60 15 49 16
+
+3.63v
+46 B9 68 00 34 50 8D FF 73 96 F7 BC 9F 00 5B 7A C0 FD 25 EF 00 00 73 54 00 F5 28 04 06 70 96 02 15 19 1C 1E 23 00 EC E0 04 D7 FD 92 FF FF FF 15 09 25 60 14 D0 16
+
+3.73v
+46 B9 68 00 34 50 8D FF 73 96 F7 BC 9F 00 5B 92 30 FD 25 EA 00 00 73 54 00 F5 28 04 06 70 96 02 15 19 1C 1E 23 00 EC E0 04 D7 FF 92 FF FF FF 15 09 25 60 14 55 16
+                                                                                                                              ^^
+                                                                                                                              MCSY
+
+voltage: ff -> 3.73v
+         fd -> 3.63v
+         f7 -> 3.33v
+         ea -> 2.68v
+
+in set options packet:
+
+46 B9 6A 00 4B 04 00 00 5A A5 FF FF FF 00 FF FF
+00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+00 00 FF A8 FF EE FF E0 FF FD 03 FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FD FF FF FF 75 BF F7 BC 9F 3A 80 16
+   ^^
+   MCSY

doc/stc15-protocol.txt

@@ -58,6 +58,11 @@ info packet
                               MCS2-4               MCSX
                            ^^
                            factory calibration adjust for 24 MHz (range 0x40)?
+
+STC15W4K56S4:
+46 B9 68 00 34 50 8D FF 73 96 F7 BC 9F 00 5B 7A C0 FD 27 ED 00 00 73 54 00 F5 28 04 06 70 96 02 15 19 1C 1E 23 00 EC E0 04 D7 EA 92 FF FF FF 15 09 25 60 14 BD 16
+                                                                                                                              ^^
+                                                                                                                              core voltage (MCSY)
          
 IAP15F2K61S2:                  
 external osc:
@@ -140,8 +145,9 @@ option packet
 
 FF FD FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF B5 FF F7 BB 9F 3A 48 16
    ^                                                                                   ^^^^^^^^^^^^^^ 
-   MCSX                                                                                MCS0-4
+   MCSX                                                                    ^^          MCS0-4
-   
+                                                                           MCSY
+                                                                           (STC15W4)
 
 MCS bytes
 ---------
@@ -154,7 +160,7 @@ RC calibration adjust
 
 0x3f + RC calibration range (0x00, 0x40, 0x80, 0xc0)
 
-### MCS2 - MCS4 and MCSX
+### MCS2 - MCS4, MCSX and MCSY
 
 See stc15-options.txt
 

doc/stc15w4k56s4.txt

@@ -0,0 +1,128 @@
+2015-12-10 23:47:44.198341: PC
+7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F
+7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F
+7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F
+7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F
+7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F
+7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F
+7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F
+7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F
+7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F
+7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F
+7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F
+7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F
+7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F
+7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F
+7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F
+7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F
+7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F 7F
+2015-12-10 23:47:48.400692: MCU
+46 B9 68
+2015-12-10 23:47:48.411946: PC
+7F
+2015-12-10 23:47:48.414811: MCU
+00 34 50
+2015-12-10 23:47:48.427644: PC
+7F
+2015-12-10 23:47:48.428894: MCU
+8D FF 73 96 F5 7B 9F FF FF FF FF FF 27 ED 00 00
+73 54 00 F5 28 04 06 70 96 02 15 19 1C 1E 23 00
+EC E0 04 D7 F8 73 BF FF FF 15 09 25 60 16 92 16
+2015-12-10 23:47:48.725370: PC
+46 B9 6A 00 20 00 0B 00 C0 80 C0 FF C0 00 80 80
+80 FF 80 00 40 80 40 FF 40 00 00 80 00 00 00 0A
+12 16 FE FE FE FE FE FE FE FE FE FE FE FE FE
+2015-12-10 23:47:49.088353: MCU
+46 B9 68
+2015-12-10 23:47:49.099586: PC
+FE
+2015-12-10 23:47:49.102589: MCU
+00 20 00
+2015-12-10 23:47:49.115089: PC
+FE
+2015-12-10 23:47:49.116479: MCU
+0B 0D 21 12 BC 18 3E 1A 05 24 FA 2F B3 34 D1 4A
+52 5E C0 52 DB 73 1A 00 00 08 7D 16
+2015-12-10 23:47:49.266317: PC
+46 B9 6A 00 20 00 0C 71 80 72 80 73 80 74 80 75
+80 76 80 6F 40 70 40 71 40 72 40 73 40 74 40 0A
+74 16 FE FE FE FE FE FE FE FE FE FE FE FE FE FE
+2015-12-10 23:47:49.650397: MCU
+46 B9 68
+2015-12-10 23:47:49.661888: PC
+FE
+2015-12-10 23:47:49.664523: MCU
+00 20 00
+2015-12-10 23:47:49.677636: PC
+FE
+2015-12-10 23:47:49.678633: MCU
+0C 23 BF 23 D3 23 E7 23 F6 24 0F 24 23 47 73 47
+B9 47 E1 48 09 48 36 48 59 09 5B 16
+2015-12-10 23:47:49.944529: PC
+46 B9 6A 00 0E 01 72 40 F6 FF 80 73 81 04 94 16
+2015-12-10 23:47:50.045100: MCU
+46 B9 68 00 07 01 00 70 16
+2015-12-10 23:47:50.116096: PC
+46 B9 6A 00 0B 05 00 00 5A A5 01 79 16
+2015-12-10 23:47:50.190036: MCU
+46 B9 68 00 07 05 00 74 16
+2015-12-10 23:47:50.255407: PC
+46 B9 6A 00 0B 03 00 00 5A A5 01 77 16
+2015-12-10 23:47:53.130695: MCU
+46 B9 68 00 0E 03 F5 28 00 A5 03 27 49 02 AE 16
+2015-12-10 23:47:53.210814: PC
+46 B9 6A 00 8B 22 00 00 5A A5 01 04 01 36 75 81
+07 12 00 6A E5 82 60 03 02 00 02 E4 78 FF F6 D8
+FD 01 02 AF 82 8F 06 1F EE 60 0F 7D 90 7E 01 1D
+BD FF 01 1E ED 4E 70 F7 80 EB 22 AF 82 DF FE 22
+E5 B0 F4 F5 B0 75 82 05 11 31 75 82 D0 11 19 E5
+B0 F4 F5 B0 75 82 64 11 19 E5 B0 F4 F5 B0 75 82
+64 11 19 E5 B0 F4 F5 B0 75 82 64 11 19 E5 B0 F4
+F5 B0 80 D6 75 82 00 22 FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF 49 E8 16
+2015-12-10 23:47:54.003906: MCU
+46 B9 68 00 08 02 54 00 C6 16
+2015-12-10 23:47:54.068777: PC
+46 B9 6A 00 8B 02 00 80 5A A5 FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF 81 F6 16
+2015-12-10 23:47:54.867956: MCU
+46 B9 68 00 08 02 54 00 C6 16
+2015-12-10 23:47:54.932281: PC
+46 B9 6A 00 8B 02 01 00 5A A5 FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF 81 77 16
+2015-12-10 23:47:55.732519: MCU
+46 B9 68 00 08 02 54 00 C6 16
+2015-12-10 23:47:55.796791: PC
+46 B9 6A 00 8B 02 01 80 5A A5 FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF 81 F7 16
+2015-12-10 23:47:56.536325: MCU
+46 B9 68 00 08 02 54 00 C6 16
+2015-12-10 23:47:56.616743: PC
+46 B9 6A 00 4B 04 00 00 5A A5 FF FF FF 00 FF FF
+00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+00 00 FF A8 FF 91 FF 20 FF FD 03 FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF EC FF FF FF 74 BF F7 BC 9F 39 51 16
+2015-12-10 23:47:57.070169: MCU
+46 B9 68 00 08 04 54 00 C8 16

stcgal/frontend.py

@@ -80,27 +80,27 @@ class StcGal:
 
         print("Loading flash: ", end="")
         sys.stdout.flush()
-        bindata = self.load_file_auto(self.opts.code_binary)
+        bindata = self.load_file_auto(self.opts.code_image)
 
         # warn if it overflows
         if len(bindata) > code_size:
-            print("WARNING: code_binary overflows into eeprom segment!", file=sys.stderr)
+            print("WARNING: code_image overflows into eeprom segment!", file=sys.stderr)
         if len(bindata) > (code_size + ee_size):
-            print("WARNING: code_binary truncated!", file=sys.stderr)
+            print("WARNING: code_image truncated!", file=sys.stderr)
             bindata = bindata[0:code_size + ee_size]
 
         # add eeprom data if supplied
-        if self.opts.eeprom_binary:
+        if self.opts.eeprom_image:
             print("Loading EEPROM: ", end="")
             sys.stdout.flush()
-            eedata = self.load_file_auto(self.opts.eeprom_binary)
+            eedata = self.load_file_auto(self.opts.eeprom_image)
             if len(eedata) > ee_size:
-                print("WARNING: eeprom_binary truncated!", file=sys.stderr)
+                print("WARNING: eeprom_image truncated!", file=sys.stderr)
                 eedata = eedata[0:ee_size]
             if len(bindata) < code_size:
                 bindata += bytes(code_size - len(bindata))
             elif len(bindata) > code_size:
-                print("WARNING: eeprom_binary overlaps code_binary!", file=sys.stderr)
+                print("WARNING: eeprom_image overlaps code_image!", file=sys.stderr)
                 bindata = bindata[0:code_size]
             bindata += eedata
 
@@ -133,7 +133,7 @@ class StcGal:
             return 1
 
         try:
-            if self.opts.code_binary:
+            if self.opts.code_image:
                 self.program_mcu()
                 return 0
             else:
@@ -166,9 +166,10 @@ class StcGal:
 
 def cli():
     # check arguments
-    parser = argparse.ArgumentParser(description="stcgal %s - an STC MCU ISP flash tool" %stcgal.__version__)
+    parser = argparse.ArgumentParser(formatter_class=argparse.RawDescriptionHelpFormatter,
-    parser.add_argument("code_binary", help="code segment binary file to flash", type=argparse.FileType("rb"), nargs='?')
+                                     description="stcgal %s - an STC MCU ISP flash tool\n(C) 2014-2015 Grigori Goronzy\nhttps://github.com/grigorig/stcgal" %stcgal.__version__)
-    parser.add_argument("eeprom_binary", help="eeprom segment binary file to flash", type=argparse.FileType("rb"), nargs='?')
+    parser.add_argument("code_image", help="code segment file to flash (BIN/HEX)", type=argparse.FileType("rb"), nargs='?')
+    parser.add_argument("eeprom_image", help="eeprom segment file to flash (BIN/HEX)", type=argparse.FileType("rb"), nargs='?')
     parser.add_argument("-P", "--protocol", help="protocol version", choices=["stc89", "stc12a", "stc12", "stc15a", "stc15"], default="stc12")
     parser.add_argument("-p", "--port", help="serial port device", default="/dev/ttyUSB0")
     parser.add_argument("-b", "--baud", help="transfer baud rate (default: 19200)", type=BaudType(), default=19200)

stcgal/protocols.py

@@ -446,13 +446,14 @@ class Stc15AOption(BaseOption):
 
 class Stc15Option(BaseOption):
     def __init__(self, msr):
-        assert len(msr) == 4
+        assert len(msr) == 5
         self.msr = bytearray(msr)
 
         self.options = (
             ("reset_pin_enabled", self.get_reset_pin_enabled, self.set_reset_pin_enabled),
             ("clock_source", self.get_clock_source, self.set_clock_source),
             ("clock_gain", self.get_clock_gain, self.set_clock_gain),
+            ("cpu_core_voltage", self.get_core_voltage, self.set_core_voltage),
             ("watchdog_por_enabled", self.get_watchdog, self.set_watchdog),
             ("watchdog_stop_idle", self.get_watchdog_idle, self.set_watchdog_idle),
             ("watchdog_prescale", self.get_watchdog_prescale, self.set_watchdog_prescale),
@@ -603,6 +604,18 @@ class Stc15Option(BaseOption):
         self.msr[2] &= 0xdf
         self.msr[2] |= 0x20 if val else 0x00
 
+    def get_core_voltage(self):
+        if self.msr[4] == 0xea: return "low"
+        elif self.msr[4] == 0xf7: return "mid"
+        elif self.msr[4] == 0xfd: return "high"
+        else: return "unknown"
+
+    def set_core_voltage(self, val):
+        volt_vals = {"low": 0xea, "mid": 0xf7, "high": 0xfd}
+        if val not in volt_vals.keys():
+            raise ValueError("must be one of %s" % list(volt_vals.keys()))
+        self.msr[4] = volt_vals[val]
+
 
 class StcBaseProtocol:
     """Basic functionality for STC BSL protocols"""
@@ -662,13 +675,17 @@ class StcBaseProtocol:
         print("Target frequency: %.3f MHz" % (self.mcu_clock_hz / 1E6))
         print("Target BSL version: %s" % self.mcu_bsl_version)
 
-    def pulse(self):
+    def pulse(self, character=b"\x7f", timeout=0):
-        """Send a sequence of 0x7f bytes for synchronization"""
+        """Send a sequence of bytes for synchronization with MCU"""
 
+        duration = 0
         while True:
-            self.ser.write(b"\x7f")
+            if timeout > 0 and duration > timeout:
+                raise serial.SerialTimeoutException("pulse timeout")
+            self.ser.write(character)
             self.ser.flush()
             time.sleep(0.015)
+            duration += 0.015
             if self.ser.inWaiting() > 0: break
 
     def initialize_model(self):
@@ -715,12 +732,18 @@ class StcBaseProtocol:
         Set up serial port, send sync sequence and get part info.
         """
 
-        self.ser = serial.Serial(port=self.port, baudrate=self.baud_handshake,
+        self.ser = serial.Serial(port=self.port,
                                  parity=self.PARITY)
+        # set baudrate separately to workaround a bug with the CH340 driver
+        # in older Linux kernels
+        self.ser.baudrate = self.baud_handshake
 
-        # conservative timeout values
+        # fast timeout values to deal with detection errors
-        self.ser.timeout = 10.0
+        self.ser.timeout = 0.5
-        self.ser.interCharTimeout = 1.0
+        self.ser.interCharTimeout = 0.5
+
+        # avoid glitches if there is something in the input buffer
+        self.ser.flushInput()
 
         print("Waiting for MCU, please cycle power: ", end="")
         sys.stdout.flush()
@@ -735,6 +758,10 @@ class StcBaseProtocol:
             except (StcFramingException, serial.SerialTimeoutException): pass
         print("done")
 
+        # conservative timeout values
+        self.ser.timeout = 15.0
+        self.ser.interCharTimeout = 1.0
+
         self.initialize_status(status_packet)
         self.initialize_model()
         self.initialize_options(status_packet)
@@ -1524,7 +1551,7 @@ class Stc15AProtocol(Stc12Protocol):
         packet += bytes([0x98, 0x00, 0x02, 0x00])
         packet += bytes([0x98, 0x80, 0x02, 0x00])
         self.write_packet(packet)
-        self.pulse()
+        self.pulse(timeout=1.0)
         response = self.read_packet()
         if response[0] != 0x65:
             raise StcProtocolException("incorrect magic in handshake packet")
@@ -1566,7 +1593,7 @@ class Stc15AProtocol(Stc12Protocol):
             packet += struct.pack(">H", target_trim_start + i)
             packet += bytes([0x02, 0x00])
         self.write_packet(packet)
-        self.pulse()
+        self.pulse(timeout=1.0)
         response = self.read_packet()
         if response[0] != 0x65:
             raise StcProtocolException("incorrect magic in handshake packet")
@@ -1627,7 +1654,7 @@ class Stc15Protocol(Stc15AProtocol):
         """Initialize options"""
 
         # create option state
-        self.options = Stc15Option(status_packet[5:8] + status_packet[12:13])
+        self.options = Stc15Option(status_packet[5:8] + status_packet[12:13] + status_packet[37:38])
         self.options.print()
 
     def initialize_status(self, packet):
@@ -1731,8 +1758,7 @@ class Stc15Protocol(Stc15AProtocol):
         packet += bytes([0x00, 0x40, 0x80, 0x40, 0xff, 0x40])
         packet += bytes([0x00, 0x00, 0x80, 0x00, 0xc0, 0x00])
         self.write_packet(packet)
-        self.ser.write(bytes([0x92, 0x92, 0x92, 0x92]))
+        self.pulse(b"\xfe", timeout=1.0)
-        self.ser.flush()
         response = self.read_packet()
         if response[0] != 0x00:
             raise StcProtocolException("incorrect magic in handshake packet")
@@ -1751,8 +1777,7 @@ class Stc15Protocol(Stc15AProtocol):
         for i in range(prog_trim[0] - 3, prog_trim[0] + 3):
             packet += bytes([i & 0xff, prog_trim[1]])
         self.write_packet(packet)
-        self.ser.write(bytes([0x92, 0x92, 0x92, 0x92]))
+        self.pulse(b"\xfe", timeout=1.0)
-        self.ser.flush()
         response = self.read_packet()
         if response[0] != 0x00:
             raise StcProtocolException("incorrect magic in handshake packet")
@@ -1880,7 +1905,7 @@ class Stc15Protocol(Stc15AProtocol):
             response = self.read_packet()
             if response[0] != 0x07 or response[1] != 0x54:
                 raise StcProtocolException("incorrect magic in finish packet")
-            print(" done")
+            print("done")
 
     def program_options(self):
         print("Setting options: ", end="")
@@ -1900,7 +1925,9 @@ class Stc15Protocol(Stc15AProtocol):
                          (self.trim_frequency >> 0) & 0xff,
                          0xff])
         packet += bytes([msr[3]])
-        packet += bytes([0xff] * 27)
+        packet += bytes([0xff] * 23)
+        packet += bytes([msr[4]])
+        packet += bytes([0xff] * 3)
         packet += bytes([self.trim_value[0], self.trim_value[1] + 0x3f])
         packet += msr[0:3]
         self.write_packet(packet)