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stc15: add core voltage option (STC15W)

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This is used on STC15W4 series and has no function on earlier MCUs.
There is no good way to filter options, unfortunately.
This commit is contained in:
Grigori Goronzy 2015-12-11 01:09:47 +01:00
parent 11b165c02c
commit 76b3418f0a
4 changed files with 63 additions and 6 deletions
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1
README.md
View File

@ -231,6 +231,7 @@ Option key | Possible values | Protocols/Models | Descri
```rstout_por_state``` | low/high | STC15+ | RSTOUT pin state after power-on reset
```uart2_passthrough``` | true/false | STC15+ | Pass-through UART1 to UART2 pins (for single-wire UART mode)
```uart2_pin_mode``` | push-pull/normal | STC15+ | Output mode of UART2 TX pin
```cpu_core_voltage``` | low/mid/high | STC15W+ | CPU core voltage (low: ~2.7V, mid: ~3.3V, high: ~3.6V)
### Frequency trimming

35
doc/stc15-options.txt
View File

@ -5,6 +5,7 @@ MCS3 is like early STC15 MCS1.
MCS2 is like early STC15 MCS2.
MCS4 is like early STC15 MCS0 but with additions.
MCSX is like early STC15 MCS12.
MCSY is new in STC15W4 series
baseline
B5 FF F7 BB 9F
@ -80,3 +81,37 @@ external oscillator enabled (IAP15F2K61S2)
external oscillator enabled + clock gain low (IAP15F2K61S2)
9C 7F F7 BB 9C
--> MCS 4 bit controls clock gain. high => high clock gain, low => low clock gain.
cpu core supply level (MCSY)
in status packet:
2.68v
46 B9 68 00 34 50 8D FF 73 96 F7 BC 9F 00 5B 7A C0 FD 27 ED 00 00 73 54 00 F5 28 04 06 70 96 02 15 19 1C 1E 23 00 EC E0 04 D7 EA 92 FF FF FF 15 09 25 60 14 BD 16
3.33v
46 B9 68 00 34 50 8D FF 73 96 F7 BC 9F 00 5B 92 30 FD 25 EA 00 FC 73 54 00 F5 28 04 06 70 96 02 15 19 1C 1E 23 00 EC E0 04 D7 F7 92 FF FF FF 15 09 25 60 15 49 16
3.63v
46 B9 68 00 34 50 8D FF 73 96 F7 BC 9F 00 5B 7A C0 FD 25 EF 00 00 73 54 00 F5 28 04 06 70 96 02 15 19 1C 1E 23 00 EC E0 04 D7 FD 92 FF FF FF 15 09 25 60 14 D0 16
3.73v
46 B9 68 00 34 50 8D FF 73 96 F7 BC 9F 00 5B 92 30 FD 25 EA 00 00 73 54 00 F5 28 04 06 70 96 02 15 19 1C 1E 23 00 EC E0 04 D7 FF 92 FF FF FF 15 09 25 60 14 55 16
^^
MCSY
voltage: ff -> 3.73v
fd -> 3.63v
f7 -> 3.33v
ea -> 2.68v
in set options packet:
46 B9 6A 00 4B 04 00 00 5A A5 FF FF FF 00 FF FF
00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
00 00 FF A8 FF EE FF E0 FF FD 03 FF FF FF FF FF
FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
FF FD FF FF FF 75 BF F7 BC 9F 3A 80 16
^^
MCSY

12
doc/stc15-protocol.txt
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@ -58,6 +58,11 @@ info packet
MCS2-4 MCSX
^^
factory calibration adjust for 24 MHz (range 0x40)?
STC15W4K56S4:
46 B9 68 00 34 50 8D FF 73 96 F7 BC 9F 00 5B 7A C0 FD 27 ED 00 00 73 54 00 F5 28 04 06 70 96 02 15 19 1C 1E 23 00 EC E0 04 D7 EA 92 FF FF FF 15 09 25 60 14 BD 16
^^
core voltage (MCSY)
IAP15F2K61S2:
external osc:
@ -140,8 +145,9 @@ option packet
FF FD FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF B5 FF F7 BB 9F 3A 48 16
^ ^^^^^^^^^^^^^^
MCSX MCS0-4
MCSX ^^ MCS0-4
MCSY
(STC15W4)
MCS bytes
---------
@ -154,7 +160,7 @@ RC calibration adjust
0x3f + RC calibration range (0x00, 0x40, 0x80, 0xc0)
### MCS2 - MCS4 and MCSX
### MCS2 - MCS4, MCSX and MCSY
See stc15-options.txt

21
stcgal/protocols.py
View File

@ -446,13 +446,14 @@ class Stc15AOption(BaseOption):
class Stc15Option(BaseOption):
def __init__(self, msr):
assert len(msr) == 4
assert len(msr) == 5
self.msr = bytearray(msr)
self.options = (
("reset_pin_enabled", self.get_reset_pin_enabled, self.set_reset_pin_enabled),
("clock_source", self.get_clock_source, self.set_clock_source),
("clock_gain", self.get_clock_gain, self.set_clock_gain),
("cpu_core_voltage", self.get_core_voltage, self.set_core_voltage),
("watchdog_por_enabled", self.get_watchdog, self.set_watchdog),
("watchdog_stop_idle", self.get_watchdog_idle, self.set_watchdog_idle),
("watchdog_prescale", self.get_watchdog_prescale, self.set_watchdog_prescale),
@ -603,6 +604,18 @@ class Stc15Option(BaseOption):
self.msr[2] &= 0xdf
self.msr[2] |= 0x20 if val else 0x00
def get_core_voltage(self):
if self.msr[4] == 0xea: return "low"
elif self.msr[4] == 0xf7: return "mid"
elif self.msr[4] == 0xfd: return "high"
else: return "unknown"
def set_core_voltage(self, val):
volt_vals = {"low": 0xea, "mid": 0xf7, "high": 0xfd}
if val not in volt_vals.keys():
raise ValueError("must be one of %s" % list(volt_vals.keys()))
self.msr[4] = volt_vals[val]
class StcBaseProtocol:
"""Basic functionality for STC BSL protocols"""
@ -1635,7 +1648,7 @@ class Stc15Protocol(Stc15AProtocol):
"""Initialize options"""
# create option state
self.options = Stc15Option(status_packet[5:8] + status_packet[12:13])
self.options = Stc15Option(status_packet[5:8] + status_packet[12:13] + status_packet[37:38])
self.options.print()
def initialize_status(self, packet):
@ -1906,7 +1919,9 @@ class Stc15Protocol(Stc15AProtocol):
(self.trim_frequency >> 0) & 0xff,
0xff])
packet += bytes([msr[3]])
packet += bytes([0xff] * 27)
packet += bytes([0xff] * 23)
packet += bytes([msr[4]])
packet += bytes([0xff] * 3)
packet += bytes([self.trim_value[0], self.trim_value[1] + 0x3f])
packet += msr[0:3]
self.write_packet(packet)