fe60e647bf
Implement option handling for STC8 series, based on STC8A8K64S4A12 reverse engineering. This mostly wraps up all important parts of the STC8 implementation. Interoperability was tested with STC-ISP V6.86O. v2: update documentation
71 lines
1.5 KiB
Plaintext
71 lines
1.5 KiB
Plaintext
MCS bytes
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=========
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46 b9 6a 00 33 04 00 00 5a a5 ff ff ff 00 ff ff
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00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
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00 ff 01 31 20 80 34 00 01 ff ff ff ff ff 8b bf
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^^^^^^^^^^^ ^^ ^^ ^^ ^^
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frequency clkdiv 5) 1) 3)
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^^^^^
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trim?
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f7 fe 1f cc 16
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^^ ^^
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4) 2)
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1) not stricty related to some register
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aka MCS1
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bit 0: ? always 1
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bit 1: oscillator high gain
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bit 2: EPWM push-pull enabled
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bit 3: p2.0 state after boot
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bit 4: TXD signal source from RXD
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bit 5: p3.7 push-pull enabled
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bit 6: UART1 remap enabled
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bit 7: long power-on reset delay
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2) not strictly related to some register
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aka MCS4
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eeprom size / code space upper limit (in pages)
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only seems to apply to devices with max. flash size
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e.g. fe -> 63.5K, e0 -> 56K
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3) like RSTCFG? inverted?
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aka MCS2
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bit 0: LVD0
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bit 1: LVD1
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bit 2: ? always 1
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bit 3: ? always 1
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bit 4: ~reset pin enabled
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bit 5: ? always 1
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bit 6: ~enable lvd reset
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bit 7: ? always 1
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LVD:
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2.20V -> 0xbf
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2.40V -> 0xbe
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2.70V -> 0xbd
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3.00V -> 0xbc
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4) like WDT_CONTR
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aka MCS3
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bit 0: WDPS0
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bit 1: WDPS1
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bit 2: WDPS2
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bit 3: ~stop wdt in idle
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bit 4: ? always 1
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bit 5: ~enable wdt on por
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bit 6: ? always 1
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bit 7: ? always 1
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WDPS like in datasheet
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5)
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aka MCS0
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bit 0: ? ~BSLD / bootloader enabled
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bit 1: erase eeprom enabled
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bit 2: ?
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bit 3: ?
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bit 4: ?
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bit 5: ?
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bit 6: ?
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bit 7: ? |