92f4def11a
Completely revamp option handling. This fixes a wrong index of MCS4, which is now renamed to MCS3. Now programming should be exactly similar to STC-ISP 6.85M. This also renames the values of the low_voltage_reset option for clarity. Also update the documentation and clarity the meaning of the option according to protocol family. Addresses grigorig/stcgal#14.
62 lines
1.5 KiB
Plaintext
62 lines
1.5 KiB
Plaintext
Model-specific configuration registers
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Placement of configuration values
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"~" means the bit is a negated boolean. Sometimes values overlap,
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depending on MCU model.
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In STC12A series, the first 7 MCS bytes have active
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values. Generally, unused bits should be set to 1.
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MCS0
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----
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MSB 7 6 5 4 3 2 1 0 LSB
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CLKSRC
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CLKSRC := clock source (0 = internal RC, 1 = external crystal)
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MCS1
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----
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MSB 7 6 5 4 3 2 1 0 LSB
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~WDEN ~WDSTP WDPS2 WDPS1 WDPS0
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~WDEN := watchdog enable after power-on-reset
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~WDSTP := stop watchdog counter in idle mode
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WDPS2 WDPS1 WDPS0 divisior
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0 0 0 2
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0 0 1 4
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0 1 0 8
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0 1 1 16
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1 0 0 32
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1 0 1 64
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1 1 0 128
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1 1 1 256
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MCS2
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----
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MSB 7 6 5 4 3 2 1 0 LSB
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~EERE ~BSLD
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~EREE := enable eeprom erase next time MCU is programmed
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~BSLD := enable BSL pin detect; i.e. BSL is only enabled if P1.0/P1.1
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(or others, depends on MCU model) are held low on POR.
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MCS3 (at index 6!)
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------------------
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MSB 7 6 5 4 3 2 1 0 LSB
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LVD
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LVD := low voltage detection threshold
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LVD threshold
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0 3.7V
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1 3.3V
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