76b3418f0a
This is used on STC15W4 series and has no function on earlier MCUs. There is no good way to filter options, unfortunately.
118 lines
3.6 KiB
Plaintext
118 lines
3.6 KiB
Plaintext
STC15 series MCS bytes
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======================
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MCS3 is like early STC15 MCS1.
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MCS2 is like early STC15 MCS2.
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MCS4 is like early STC15 MCS0 but with additions.
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MCSX is like early STC15 MCS12.
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MCSY is new in STC15W4 series
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baseline
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B5 FF F7 BB 9F
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long por disabled
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B6 FF F7 BB 1F
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--> MCS4 bit 7 controls POR delay. low => short, high => long
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reset pin as io disabled
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B8 FF F7 BB 8F
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--> MCS4 bit 4 controls reset pin. low => reset is normal, high => reset is io
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low voltage reset disabled
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B6 FF F7 FB 9F
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--> MCS3 bit 6 controls low voltage reset. low => lv reset enabled, high => disabled
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lvd threshold 2.61v
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B8 FF F7 BA 9F
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lvd threshold 2.82v
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B5 FF F7 B9 9F
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lvd threshold 3.08v
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B6 FF F7 B8 9F
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--> MCS3 bits 0-2 control LVD threshold setting. exact mapping not yet clear.
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eeprom lv inhibit disabled
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B7 FF F7 3B 9F
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--> MCS3 bit 7 controls eeprom lv inhibit. high => eeprom lv inhibit enabled, low => disabled
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watchdog after reset enabled
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B6 FF D7 BB 9F
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--> MCS2 bit 5 controls watchdog after reset. high => disabled, low => enabled
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watchdog prescaler 128
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B4 FF F6 BB 9F
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watchdog prescaler 64
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B5 FF F5 BB 9F
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watchdog prescaler 32
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B5 FF F4 BB 9F
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watchdog prescaler 2
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B6 FF F0 BB 9F
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--> MCS2 bits 0-2 control watchdog prescaler. mapping is similar to early STC15.
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wdt stop in idle disabled
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B7 FF FF BB 9F
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erase eeprom next programming
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B4 FF F7 BB 9F
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--> it's somewhere else! it's bit 1 of the extra MCSX byte that is typically 0xfd. low => erase eeprom disabled, high => erase eeprom enabled
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p3.3 por state enabled
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B9 FF F7 BB 97
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--> MCS4 bit 3 controls the p3.3 state. high => p3.3 high, low => p3.3 low
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p3.1 passthrough from p3.0 enabled
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B5 FF F7 BB DF
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--> MCS4 bit 2 controls the p3.1 passthrough. low => passthrough disabled, high => passthrough enabled
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p3.1 push pull enabled
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B5 FF F7 BB BF
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--> MCS4 bit 1 controls p3.1 push pull. low => quasi-bidi, high => push-pull
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bsl pindetect enabled
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B5 FF F7 BB BF
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--> somewhere else, MCSX bit 0. low => pindetect enabled, high => pindetect disabled.
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external oscillator enabled (IAP15F2K61S2)
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9C 7F F7 BB 9E
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--> MCS4 bit 0 controls external oscillator. low => use external crystal, high => use RC.
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external oscillator enabled + clock gain low (IAP15F2K61S2)
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9C 7F F7 BB 9C
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--> MCS 4 bit controls clock gain. high => high clock gain, low => low clock gain.
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cpu core supply level (MCSY)
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in status packet:
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2.68v
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46 B9 68 00 34 50 8D FF 73 96 F7 BC 9F 00 5B 7A C0 FD 27 ED 00 00 73 54 00 F5 28 04 06 70 96 02 15 19 1C 1E 23 00 EC E0 04 D7 EA 92 FF FF FF 15 09 25 60 14 BD 16
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3.33v
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46 B9 68 00 34 50 8D FF 73 96 F7 BC 9F 00 5B 92 30 FD 25 EA 00 FC 73 54 00 F5 28 04 06 70 96 02 15 19 1C 1E 23 00 EC E0 04 D7 F7 92 FF FF FF 15 09 25 60 15 49 16
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3.63v
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46 B9 68 00 34 50 8D FF 73 96 F7 BC 9F 00 5B 7A C0 FD 25 EF 00 00 73 54 00 F5 28 04 06 70 96 02 15 19 1C 1E 23 00 EC E0 04 D7 FD 92 FF FF FF 15 09 25 60 14 D0 16
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3.73v
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46 B9 68 00 34 50 8D FF 73 96 F7 BC 9F 00 5B 92 30 FD 25 EA 00 00 73 54 00 F5 28 04 06 70 96 02 15 19 1C 1E 23 00 EC E0 04 D7 FF 92 FF FF FF 15 09 25 60 14 55 16
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^^
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MCSY
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voltage: ff -> 3.73v
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fd -> 3.63v
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f7 -> 3.33v
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ea -> 2.68v
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in set options packet:
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46 B9 6A 00 4B 04 00 00 5A A5 FF FF FF 00 FF FF
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00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
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00 00 FF A8 FF EE FF E0 FF FD 03 FF FF FF FF FF
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FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
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FF FD FF FF FF 75 BF F7 BC 9F 3A 80 16
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^^
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MCSY
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