frontend: also catch I/O errors in pulse phase

The cpu core voltage setting is only available on newer parts, so do not
try to support it on older ones. The option packet is too short on some
parts, which resulted in an assertion hit.

There may be a nicer solution, but this works for now.

Fixes grigorig/stcgal#6.

stcgal/frontend.py

@@ -131,6 +131,10 @@ class StcGal:
             sys.stdout.flush();
             print("Serial port error: %s" % e, file=sys.stderr)
             return 1
+        except IOError as e:
+            sys.stdout.flush();
+            print("I/O error: %s" % e, file=sys.stderr)
+            return 1
 
         try:
             if self.opts.code_image:

stcgal/protocols.py

@@ -446,14 +446,13 @@ class Stc15AOption(BaseOption):
 
 class Stc15Option(BaseOption):
     def __init__(self, msr):
-        assert len(msr) == 5
+        assert len(msr) >= 4
         self.msr = bytearray(msr)
 
         self.options = (
             ("reset_pin_enabled", self.get_reset_pin_enabled, self.set_reset_pin_enabled),
             ("clock_source", self.get_clock_source, self.set_clock_source),
             ("clock_gain", self.get_clock_gain, self.set_clock_gain),
-            ("cpu_core_voltage", self.get_core_voltage, self.set_core_voltage),
             ("watchdog_por_enabled", self.get_watchdog, self.set_watchdog),
             ("watchdog_stop_idle", self.get_watchdog_idle, self.set_watchdog_idle),
             ("watchdog_prescale", self.get_watchdog_prescale, self.set_watchdog_prescale),
@@ -468,6 +467,9 @@ class Stc15Option(BaseOption):
             ("uart2_pin_mode", self.get_uart_pin_mode, self.set_uart_pin_mode),
         )
 
+        if len(msr) > 4:
+            self.options += ("cpu_core_voltage", self.get_core_voltage, self.set_core_voltage),
+
     def get_reset_pin_enabled(self):
         return not bool(self.msr[2] & 16)
 
@@ -1925,7 +1927,10 @@ class Stc15Protocol(Stc15AProtocol):
                          0xff])
         packet += bytes([msr[3]])
         packet += bytes([0xff] * 23)
+        if len(msr) > 4:
             packet += bytes([msr[4]])
+        else:
+            packet += bytes([0xff])
         packet += bytes([0xff] * 3)
         packet += bytes([self.trim_value[0], self.trim_value[1] + 0x3f])
         packet += msr[0:3]