stc8: implement option handling

Implement option handling for STC8 series, based on STC8A8K64S4A12
reverse engineering.

This mostly wraps up all important parts of the STC8 implementation.

Interoperability was tested with STC-ISP V6.86O.

v2: update documentation

doc/stc8-options.txt

@@ -0,0 +1,71 @@
+MCS bytes
+=========
+
+            46 b9 6a 00 33 04 00 00 5a a5 ff ff ff 00 ff ff
+            00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
+            00 ff 01 31 20 80 34 00 01 ff ff ff ff ff 8b bf
+                  ^^^^^^^^^^^       ^^    ^^          ^^ ^^
+                  frequency         clkdiv 5)         1) 3)
+                              ^^^^^
+                              trim?
+            f7 fe 1f cc 16
+            ^^ ^^
+            4) 2)
+
+1) not stricty related to some register
+aka MCS1
+bit 0: ? always 1
+bit 1: oscillator high gain
+bit 2: EPWM push-pull enabled
+bit 3: p2.0 state after boot
+bit 4: TXD signal source from RXD
+bit 5: p3.7 push-pull enabled
+bit 6: UART1 remap enabled
+bit 7: long power-on reset delay
+
+2) not strictly related to some register
+aka MCS4
+eeprom size / code space upper limit (in pages)
+only seems to apply to devices with max. flash size
+e.g. fe -> 63.5K, e0 -> 56K
+
+3) like RSTCFG? inverted?
+aka MCS2
+bit 0: LVD0
+bit 1: LVD1
+bit 2: ? always 1
+bit 3: ? always 1
+bit 4: ~reset pin enabled
+bit 5: ? always 1
+bit 6: ~enable lvd reset
+bit 7: ? always 1
+
+LVD:
+2.20V -> 0xbf
+2.40V -> 0xbe
+2.70V -> 0xbd
+3.00V -> 0xbc
+
+4) like WDT_CONTR
+aka MCS3
+bit 0: WDPS0
+bit 1: WDPS1
+bit 2: WDPS2
+bit 3: ~stop wdt in idle
+bit 4: ? always 1
+bit 5: ~enable wdt on por
+bit 6: ? always 1
+bit 7: ? always 1
+
+WDPS like in datasheet
+
+5)
+aka MCS0
+bit 0: ? ~BSLD / bootloader enabled
+bit 1: erase eeprom enabled
+bit 2: ?
+bit 3: ?
+bit 4: ?
+bit 5: ?
+bit 6: ?
+bit 7: ?

doc/stc8-protocol.txt

@@ -31,6 +31,10 @@ Clock set to 20 MHz by STC-ISP (encoding is different compared to STC15):
                                       ^^ clkdiv
                     ^^^^^^^^^^^ clk
 
+MCS bytes
+
+46 B9 68 00 30   50 01 31 2E 90 38 01 01 FF FD 8B BF FF 27 35 F7 FE 73 55 00 F6 28 09 85 E3 5F 80 07 20 20 20 01 00 00 FE 05 3A 17 05 25 91 FF   10 54 16
+                                            ^^^^^^^^          ^^^^^
 
 Disconnect
 ----------