71 lines
1.9 KiB
Plaintext
71 lines
1.9 KiB
Plaintext
|
Model-specific configuration registers
|
||
|
|
Placement of configuration values
|
||
|
|
|
||
|
|
"~" means the bit is a negated boolean. Sometimes values overlap,
|
||
|
|
depending on MCU model.
|
||
|
|
|
||
|
|
In STC10/11/12 series, the first 4 MCS bytes have active
|
||
|
|
values. Generally, unused bits should be set to 1.
|
||
|
|
|
||
|
|
|
||
|
|
MCS0
|
||
|
|
----
|
||
|
|
|
||
|
|
MSB 7 6 5 4 3 2 1 0 LSB
|
||
|
|
~RS2LV OSC1 OSC0 RSPEN
|
||
|
|
~LVD
|
||
|
|
|
||
|
|
RSPEN := RESET pin enable
|
||
|
|
~RS2LV := RESET2 pin low voltage detect enable
|
||
|
|
~LVD := low voltage detect enable
|
||
|
|
OSC0, OSC1 := oscillator stabilization delay
|
||
|
|
|
||
|
|
OSC1 OSC0 delay
|
||
|
|
0 0 4096
|
||
|
|
0 1 8192
|
||
|
|
1 0 16384
|
||
|
|
1 1 32768
|
||
|
|
|
||
|
|
|
||
|
|
MCS1
|
||
|
|
----
|
||
|
|
|
||
|
|
MSB 7 6 5 4 3 2 1 0 LSB
|
||
|
|
~PORD OSCG CLKSRC
|
||
|
|
|
||
|
|
~PORD := power-on-reset (POR) delay (0 = long, 1 = short)
|
||
|
|
OSCG := high oscillator gain
|
||
|
|
CLKSRC := clock source (0 = internal RC, 1 = external crystal)
|
||
|
|
|
||
|
|
|
||
|
|
MCS2
|
||
|
|
----
|
||
|
|
|
||
|
|
MSB 7 6 5 4 3 2 1 0 LSB
|
||
|
|
~WDEN ~WDSTP WDPS2 WDPS1 WDPS0
|
||
|
|
|
||
|
|
~WDEN := watchdog enable after power-on-reset
|
||
|
|
~WDSTP := stop watchdog counter in idle mode
|
||
|
|
WDPS2...WDPS0 := watchdog counter prescaler
|
||
|
|
|
||
|
|
WDPS2 WDPS1 WDPS0 divisior
|
||
|
|
0 0 0 2
|
||
|
|
0 0 1 4
|
||
|
|
0 1 0 8
|
||
|
|
0 1 1 16
|
||
|
|
1 0 0 32
|
||
|
|
1 0 1 64
|
||
|
|
1 1 0 128
|
||
|
|
1 1 1 256
|
||
|
|
|
||
|
|
|
||
|
|
MCS3
|
||
|
|
----
|
||
|
|
|
||
|
|
MSB 7 6 5 4 3 2 1 0 LSB
|
||
|
|
~EREE ~BSLD
|
||
|
|
|
||
|
|
~EREE := enable eeprom erase next time MCU is programmed
|
||
|
|
~BSLD := enable BSL pin detect; i.e. BSL is only enabled if P1.0/P1.1
|
||
|
|
(or others, depends on MCU model) are held low on POR.
|