67 lines
1.5 KiB
Plaintext
67 lines
1.5 KiB
Plaintext
|
Model-specific configuration registers
|
||
|
|
Placement of configuration values
|
||
|
|
|
||
|
|
"~" means the bit is a negated boolean. Sometimes values overlap,
|
||
|
|
depending on MCU model.
|
||
|
|
|
||
|
|
In STC12A series, the first 4 MCS bytes have active
|
||
|
|
values. Generally, unused bits should be set to 1.
|
||
|
|
|
||
|
|
MCS0
|
||
|
|
----
|
||
|
|
|
||
|
|
MSB 7 6 5 4 3 2 1 0 LSB
|
||
|
|
CLKSRC
|
||
|
|
|
||
|
|
CLKSRC := clock source (0 = internal RC, 1 = external crystal)
|
||
|
|
|
||
|
|
|
||
|
|
MCS1
|
||
|
|
----
|
||
|
|
|
||
|
|
MSB 7 6 5 4 3 2 1 0 LSB
|
||
|
|
~WDEN ~WDSTP WDPS2 WDPS1 WDPS0
|
||
|
|
|
||
|
|
~WDEN := watchdog enable after power-on-reset
|
||
|
|
~WDSTP := stop watchdog counter in idle mode
|
||
|
|
|
||
|
|
WDPS2 WDPS1 WDPS0 divisior
|
||
|
|
0 0 0 2
|
||
|
|
0 0 1 4
|
||
|
|
0 1 0 8
|
||
|
|
0 1 1 16
|
||
|
|
1 0 0 32
|
||
|
|
1 0 1 64
|
||
|
|
1 1 0 128
|
||
|
|
1 1 1 256
|
||
|
|
|
||
|
|
|
||
|
|
MCS2
|
||
|
|
----
|
||
|
|
|
||
|
|
MSB 7 6 5 4 3 2 1 0 LSB
|
||
|
|
~EERE ~BSLD
|
||
|
|
|
||
|
|
~EREE := enable eeprom erase next time MCU is programmed
|
||
|
|
~BSLD := enable BSL pin detect; i.e. BSL is only enabled if P1.0/P1.1
|
||
|
|
(or others, depends on MCU model) are held low on POR.
|
||
|
|
|
||
|
|
|
||
|
|
MCS3
|
||
|
|
----
|
||
|
|
|
||
|
|
Unused.
|
||
|
|
|
||
|
|
|
||
|
|
MCS4
|
||
|
|
----
|
||
|
|
|
||
|
|
MSB 7 6 5 4 3 2 1 0 LSB
|
||
|
|
LVD
|
||
|
|
|
||
|
|
LVD := low voltage detection threshold
|
||
|
|
|
||
|
|
LVD threshold
|
||
|
|
0 3.7V
|
||
|
|
1 3.3V
|