2018-08-31 20:52:35 +02:00
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Usage
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=====
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Call stcgal with ```-h``` for usage information.
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```
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usage: stcgal [-h] [-e] [-a] [-A {dtr,rts}] [-r RESETCMD]
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[-P {stc89,stc12a,stc12b,stc12,stc15a,stc15,stc8,stc8d,stc8g,usb15,auto}]
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[-p PORT] [-b BAUD] [-l HANDSHAKE] [-o OPTION] [-t TRIM] [-D]
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[-V]
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[code_image] [eeprom_image]
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2018-08-31 20:52:35 +02:00
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2023-06-02 09:55:36 +02:00
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stcgal 1.7 - an STC MCU ISP flash tool
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2018-09-24 22:51:57 +02:00
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(C) 2014-2018 Grigori Goronzy and others
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https://github.com/grigorig/stcgal
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positional arguments:
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code_image code segment file to flash (BIN/HEX)
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eeprom_image eeprom segment file to flash (BIN/HEX)
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options:
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-h, --help show this help message and exit
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-e, --erase only erase flash memory
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-a, --autoreset cycle power automatically by asserting DTR
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-A {dtr,rts,dtr_inverted,rts_inverted}, --resetpin {dtr,rts,dtr_inverted,rts_inverted}
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pin to hold down when using --autoreset (default: DTR)
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-r RESETCMD, --resetcmd RESETCMD
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shell command for board power-cycling (instead of DTR
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assertion)
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-P {stc89,stc12a,stc12b,stc12,stc15a,stc15,stc8,stc8d,stc8g,usb15,auto}, --protocol {stc89,stc12a,stc12b,stc12,stc15a,stc15,stc8,stc8d,stc8g,usb15,auto}
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protocol version (default: auto)
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-p PORT, --port PORT serial port device
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-b BAUD, --baud BAUD transfer baud rate (default: 115200)
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-l HANDSHAKE, --handshake HANDSHAKE
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handshake baud rate (default: 2400)
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-o OPTION, --option OPTION
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set option (can be used multiple times, see
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documentation)
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-t TRIM, --trim TRIM RC oscillator frequency in kHz (STC15+ series only)
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-D, --debug enable debug output
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-V, --version print version info and exit
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```
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Most importantly, ```-p``` sets the serial port to be used for programming.
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### Transfer baud rate
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The default value of 115200 Baud is supported by all MCU starting with
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the STC15 family, and at least the STC12C5A56S2 before that. For older
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MCU, you might have to use ```-b 19200``` for correct operation.
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2018-08-31 20:52:35 +02:00
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### Protocols
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STC MCUs use a variety of related but incompatible protocols for the
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BSL. The protocol can be specified with the ```-P``` flag. By default
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UART protocol autodetection is used. The mapping between protocols
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and MCU series is as follows:
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* ```auto``` Automatic detection of UART based protocols (default)
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* ```stc89``` STC89/90 series
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* ```stc89a``` STC89/90 series (BSL 7.2.5C)
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* ```stc12a``` STC12x052 series and possibly others
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* ```stc12b``` STC12x52 series, STC12x56 series and possibly others
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* ```stc12``` Most STC10/11/12 series
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* ```stc15a``` STC15x104E and STC15x204E(A) series
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* ```stc15``` Most STC15 series
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* ```stc8``` STC8A8K64S4A12 and STC8F series
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* ```stc8d``` All STC8 and STC32 series
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* ```stc8g``` STC8G1 and STC8H1 series
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* ```usb15``` USB support on STC15W4 series
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The text files in the doc/reverse-engineering subdirectory provide an
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overview over the reverse engineered protocols used by the BSLs. For
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more details, please read the source code.
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### Getting MCU information
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Call stcgal without any file to program. It will dump information
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about the MCU, e.g.:
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```
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$ ./stcgal.py -P stc15
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Waiting for MCU, please cycle power: done
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Target model:
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Name: IAP15F2K61S2
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Magic: F449
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Code flash: 61.0 KB
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EEPROM flash: 0.0 KB
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Target frequency: 10.046 MHz
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Target BSL version: 7.1S
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Target wakeup frequency: 34.771 KHz
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Target options:
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reset_pin_enabled=False
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clock_source=internal
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clock_gain=high
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watchdog_por_enabled=False
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watchdog_stop_idle=True
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watchdog_prescale=256
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low_voltage_reset=True
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low_voltage_threshold=3
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eeprom_lvd_inhibit=True
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eeprom_erase_enabled=False
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bsl_pindetect_enabled=False
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por_reset_delay=long
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rstout_por_state=high
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uart2_passthrough=False
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uart2_pin_mode=normal
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Disconnected!
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```
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If the identification fails, see the [FAQ](FAQ.md) for troubleshooting.
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2018-08-31 20:52:35 +02:00
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### Program the flash memory
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stcgal supports Intel HEX encoded files as well as binary files. Intel
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HEX is autodetected by file extension (.hex, .ihx or .ihex).
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Call stcgal just like before, but provide the path to the code image:
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```
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$ ./stcgal.py -P stc15 hello.hex
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Waiting for MCU, please cycle power: done
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Target model:
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Name: IAP15F2K61S2
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Magic: F449
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Code flash: 61.0 KB
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EEPROM flash: 0.0 KB
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Target frequency: 10.046 MHz
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Target BSL version: 7.1S
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Target wakeup frequency: 34.771 KHz
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Target options:
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reset_pin_enabled=False
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clock_source=internal
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clock_gain=high
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watchdog_por_enabled=False
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watchdog_stop_idle=True
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watchdog_prescale=256
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low_voltage_reset=True
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low_voltage_threshold=3
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eeprom_lvd_inhibit=True
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eeprom_erase_enabled=False
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bsl_pindetect_enabled=False
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por_reset_delay=long
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rstout_por_state=high
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uart2_passthrough=False
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uart2_pin_mode=normal
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Loading flash: 80 bytes (Intel HEX)
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Trimming frequency: 10.046 MHz
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Switching to 19200 baud: done
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Erasing flash: done
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Writing 256 bytes: .... done
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Setting options: done
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Target UID: 0D000021022632
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Disconnected!
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```
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You can also program the EEPROM part of the memory, if applicable. Add
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the EEPROM image path to the commandline after the flash image path.
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stcgal uses a conservative baud rate of 19200 bps by
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default. Programming can be sped up by choosing a faster baud rate
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with the flag ```-b```.
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### Device options
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stcgal dumps a number of target options. These can be modified as
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well. Provide one (or more) ```-o``` flags followed by a key-value
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pair on the commandline to adjust these settings. For instance, you can
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enable the external crystal as clock source:
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```
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$ ./stcgal.py -P stc15 -o clock_source=external hello.bin
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```
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Please note that device options can only be set when flash memory is
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programmed!
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#### Option keys
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Not all parts support all options. The protocols or parts that support each option are listed in the description.
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Option key | Possible values | Protocols/Models | Description
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------------------------------|-------------------|---------------------|------------
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```cpu_6t_enabled``` | true/false | STC89 only | 6T fast mode
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```bsl_pindetect_enabled``` | true/false | All | BSL only enabled when P3.2/P3.3 or P1.0/P1.1 (depends on model) are low
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```eeprom_erase_enabled``` | true/false | All | Erase EEPROM with next programming cycle
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```clock_gain``` | low/high | All with XTAL pins | Clock gain for external crystal
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```ale_enabled``` | true/false | STC89 only | ALE pin enabled if true, normal GPIO if false
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```xram_enabled``` | true/false | STC89 only | Use internal XRAM (STC89 only)
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```watchdog_por_enabled``` | true/false | All | Watchdog state after power-on reset (POR)
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```low_voltage_reset``` | low/high | STC12A/STC12 | Low-voltage reset level (low: ~3.3V, high: ~3.7V)
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```low_voltage_reset``` | true/false | STC12 | Enable RESET2 pin low voltage detect
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```low_voltage_reset``` | true/false | STC15A | Enable low-voltage reset (brownout)
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```clock_source``` | internal/external | STC12A+ with XTAL | Use internal (RC) or external (crystal) clock
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```watchdog_stop_idle``` | true/false | STC12A+ | Stop watchdog in IDLE mode
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```watchdog_prescale``` | 2,4,8,...,256 | STC12A+ | Watchdog timer prescaler, must be a power of two.
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```reset_pin_enabled``` | true/false | STC12+ | RESET pin enabled if true, normal GPIO if false
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```oscillator_stable_delay``` | 4096,...,32768 | STC11F series only | Crystal stabilization delay in clocks. Must be a power of two.
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```por_reset_delay``` | short/long | STC12+ | Power-on reset (POR) delay
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```low_voltage_threshold``` | 0...7 | STC15A+ | Low-voltage detection threshold. Model specific.
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```eeprom_lvd_inhibit``` | true/false | STC15A+ | Ignore EEPROM writes in low-voltage situations
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```rstout_por_state``` | low/high | STC15+ | RSTOUT/RSTSV pin state after power-on reset
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```uart1_remap``` | true/false | STC8 | Remap UART1 pins (P3.0/P3.1) to UART2 pins (P3.6/P3.7)
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```uart2_passthrough``` | true/false | STC15+ | Pass-through UART1 to UART2 pins (for single-wire UART mode)
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```uart2_pin_mode``` | push-pull/normal | STC15+ | Output mode of UART2 TX pin
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```cpu_core_voltage``` | low/mid/high | STC15W+ | CPU core voltage (low: ~2.7V, mid: ~3.3V, high: ~3.6V)
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```epwm_open_drain``` | true/false | STC8 | Use open-drain pin mode for EPWM pins after power-on reset
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```program_eeprom_split``` | 512 - 65024 | STC8A8 w/ 64 KB | Select split between code flash and EEPROM flash (in 512 byte blocks)
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### Frequency trimming
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If the internal RC oscillator is used (```clock_source=internal```),
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stcgal can execute a trim procedure to adjust it to a given value. This
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is only supported by STC15 series and newer. The trim values are stored
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with device options. Use the ```-t``` flag to request trimming to a certain
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value. Generally, frequencies between 4000 and 30000 kHz can be achieved.
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If trimming fails, stcgal will abort.
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### Automatic power-cycling
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STC's microcontrollers require a power-on reset to invoke the bootloader,
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which can be inconvenient. stcgal can use the DTR control signal of a
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serial interface to automate this. The DTR signal is asserted for
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approximately 500 ms when the autoreset feature is enabled with the
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```-a``` flag. This requires external circuitry to actually switch the
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power. In some cases, when the microcontroller draws only little power,
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it is possible to directly supply power from the DTR signal.
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As an alternative to DTR, you can use a custom shell command or an external
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script (via -r option) to reset the device. You should specify the command
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along with -a option. Do not forget the quotes!
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Example:
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```
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$ ./stcgal.py -P stc15 -a -r "echo 1 > /sys/class/gpio/gpio666/value"
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```
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or
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```
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$ ./stcgal.py -P stc15 -a -r "./powercycle.sh"
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```
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### Exit status
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The exit status is 0 if no error occured while executing stcgal. Any
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error, such as a protocol error or I/O error, results in an exit
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status of 1. If the the user aborted stcgal by pressing CTRL-C,
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that results in an exit status of 2.
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### USB support
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STC15W4 series have an USB-based BSL that can be optionally
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used. USB support in stcgal is experimental and might change in the
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future. USB mode is enabled by using the ```usb15``` protocol. The
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port (```-p```) flag as well as the baudrate options are ignored for
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the USB protocol. RC frequency trimming is not supported.
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